Amplifier circuit and the controlling method thereof

ABSTRACT

An amplifier circuit includes a first unit and a second unit. The first unit has a first amplifying unit, wherein the first amplifying unit provides a first main circuit unit and a first assistant circuit unit, and the first assistant circuit unit is configured for assisting the linearity of the first main circuit unit. The second unit includes a second amplifying unit, wherein the second amplifying unit has a second main circuit unit and a second assistant circuit unit, and the second assistant circuit unit is configured for assisting the linearity of the second main circuit unit. The first amplifying unit is configured for conducting in one half cycle of an input signal, and the second amplifying unit is configured for conducting in the other half cycle of the input signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

Not applicable.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not applicable.

NAMES OF THE PARTIES TO A JOINT RESEARCH AGREEMENT

Not applicable.

INCORPORATION-BY-REFERENCE OF MATERIALS SUBMITTED ON A COMPACT DISC

Not applicable.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates to an amplifier circuit and a controllingmethod thereof.

2. Description of Related Art Including Information Disclosed Under 37CFR 1.97 and 37 CFR 1.98.

With the development of the wireless communication system developingfrom the second generation (2G) wireless network, to the thirdgeneration (3G) wireless network, to the new fourth generation (4G)wireless network, a big challenge that portable system designersencounter is to design a system supporting numerous wirelesscommunication standards including the global system for mobilecommunications (GPRS), general packet radio service (GPRS), enhanceddata rates for global evolution (EDGE), code division multiple access(CDMA), wideband CDMA (WCDMA) and wireless fidelity (Wi-Fi), such asIEEE 802.11 and the related standards. Also, the communication systemsusing a 4G topology require capability to operate in multiplefrequencies and multiple modes and support of a multiple-inputmultiple-output (MIMO) antenna structure. However, the power source ofmost portable systems is a battery. Therefore, with the trend towarddesign of more complicated circuits and increasing number of devices,integrating modules in a system to a single chip and increasing batterylifetime are becoming important issues in portable system design.

In a portable wireless communication system, a baseband processor and aradio frequency receiver can now be integrated into a single chip.However, a radio frequency (RF) power amplifier (PA), which consumes themost power in the chip, is implemented by gallium-arsenide (GaAs)technology, and thus it cannot be integrated in the single chip. Theknown semi-insulative property of the GaAs material can largely reduceparasitic resistance in the base, making the GaAs material well-suitedfor the application of high frequency circuits. However, GaAs technologyexhibits relatively low yields and high costs in manufacturing. Inaddition, such technology cannot implement a system-on-chip structure.Therefore, with the recent improvement of the CMOS technology, more andmore chip designers are attempting to design RF power amplifiers by theCMOS technology.

The considerations in the design of an RF power amplifier in general arethe linearity and the power efficiency. In general, the power efficiencyis maximum when the RF power amplifier operates in or near thesaturation region. However, in order to modulate an RF signal having aninconsistent envelope, the RF power amplifier usually operates atseveral dB of back-off out power from 1 dB gain compression point orpeak power so as to insure it works at the linear region. The RF poweramplifier operated in the linear region has lower power efficiency, andthus suffers from reduced battery life of the portable system.

The factors causing the non-linearity of the power amplifier in generalare the even-order harmonic and odd-order harmonic, wherein theeven-order harmonic includes a second-order harmonic, which is usuallythe primary portion of the total harmonic distortion. FIG. 1 shows ablock diagram of a conventional RF power amplifier 10 configured tosuppress the second-order harmonic. Referring to FIG. 1, an input signalfrom an input terminal 11 is split through an input balun 12 into twosignals S1 and S2, each having equal power and phase difference of 180degrees with respect to each other. Signals S1 and S2 are transmitted tofirst and second input matching circuits 13 and 14, respectively, toobtain impedance matching, and then transmitted to first and secondamplifiers 15 and 16, respectively. Next, the output signals of thefirst and second amplifiers 15 and 16 are transmitted to first andsecond output matching circuits 17 and 18, respectively, to obtainimpedance matching, and transmitted to an output balun 19. The splitsignals S1 and S2 are combined in phase via the output balun 19 and thecombined signal is outputted from an output terminal 20. Referring toFIG. 1, the conventional RF power amplifier 10 requires two baluns 12and 19 to split and combine a signal.

US publication No. 2006/0049876 discloses an active circuit 22 havingimproved linearity using multiple gated transistors, wherein the activecircuit 22 is a common gate circuit. Referring to FIG. 2, the activecircuit 22 comprises a main circuit 24 and an assistant circuit 26. Themain circuit 24 comprises a transistor M₁ and a capacitor C_(A), and theassistant circuit 26 comprises a transistor M₂ and a capacitor C_(B).The third-order harmonic of the active circuit 22 is suppressed via theassistant circuit 26; however, the second-order harmonic of the activecircuit 22 requires an additional balun to be suppressed.

A conventional balun occupies a large chip area, and the powerconsumption of the balun reduces the overall efficiency of the chip.Therefore, it is desirable to provide an amplifier circuit havingimproved linearity and to provide a design for improving the powerefficiency of the amplifying circuit and for increasing the batterylife.

BRIEF SUMMARY OF THE INVENTION

According to one embodiment, providing an amplifier circuit comprises afirst unit and a second unit. The first unit comprises a firstamplifying unit, wherein the first amplifying unit comprises a firstmain circuit unit and a first assistant circuit unit, and the firstassistant circuit unit is configured for assisting the linearity of thefirst main circuit unit. The second unit comprises a second amplifyingunit, wherein the second amplifying unit comprises a second main circuitunit and a second assistant circuit unit, and the second assistantcircuit unit is configured for assisting the linearity of the secondmain circuit unit. The first amplifying unit is configured forconducting in one half cycle of an input signal, and the secondamplifying unit is configured for conducting in the other half cycle ofthe input signal.

According to one embodiment, providing a method for improving thelinearity of an amplifier circuit comprises the steps of: receiving aninput signal; conducting a first amplifying unit in one half cycle ofthe input signal and cutting off a second amplifying unit; cutting offthe first amplifying unit in the other half cycle of the input signaland conducting the second amplifying unit; receiving a first controlsignal for adjusting the linearity of the first amplifying unit when thefirst amplifying unit conducts; and receiving a second control signalfor adjusting the linearity of the second amplifying unit when thesecond amplifying unit conducts.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 shows a block diagram of a conventional RF power amplifierconfigured to suppress the second-order harmonic.

FIG. 2 shows a schematic view of an active circuit having improvedlinearity using multiple gated transistors.

FIG. 3 shows a block diagram of an amplifier circuit according to oneembodiment.

FIG. 4 shows a block diagram of the first amplifying unit according toone embodiment.

FIG. 5 shows a block diagram of the second amplifying unit according toone embodiment.

FIG. 6 shows a graph illustrating first and second order derivatives(gm′ and gm″) of the trans-conductance of the NMOS transistor N₁ withrespect to voltage V_(gs).

FIG. 7 shows a block diagram of the first amplifying unit according toanother embodiment.

FIG. 8 shows a block diagram of the first amplifying unit according toyet another embodiment.

FIG. 9 shows a block diagram of the second amplifying unit according toyet another embodiment.

FIG. 10(A) shows a simulation result of the output power Pout, gain,power added efficiency (PAE) of the amplifier circuit according to yetanother embodiment.

FIG. 10(B) shows a comparison result of the amplifier circuit with theprior art 1 and prior art 2 arrangements.

DETAILED DESCRIPTION OF THE INVENTION

Exemplary Embodiments will now be described more fully with reference tothe accompanying drawings. The embodiments may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the embodiments to those skilled in the art.

FIG. 3 shows a block diagram of an amplifier circuit 30 according to oneembodiment. The amplifier circuit 30 comprises a first unit 32 and asecond unit 34. The first unit 32 is configured to conduct in one halfcycle of an input signal, and the second unit 34 is configured toconduct in the other half cycle of the input signal. Referring to FIG.3, the first unit 32 comprises a first input matching circuit 36, afirst amplifying unit 38, and a first output matching circuit 40, andthe second unit 34 comprises a second input matching circuit 37, asecond amplifying unit 39, and a second output matching circuit 41. Inone embodiment, the first and second amplifying units 38 and 39 arepush-pull architectures.

Referring to FIG. 3, the first and second input matching circuits 36 and37 are disposed between an input terminal and the first and secondamplifying units 38 and 39, and thus the input impedances of the firstand second amplifying units 38 and 39 can match impedance with the inputterminal and avoid an input signal Vin being reflected to the point oforigin, resulting in the loss of the input power. The first and secondoutput matching circuits 40 and 41 are disposed between an outputterminal and the first and second amplifying units 38 and 39, and thusthe output impedances of the first and second amplifying units 38 and 39can match impedance with the system load impedance of the outputterminal. And the matching circuits 40 and 41 are provided with phasetuning function in order to coherence the output signal from amplifyingunits 38 and 39. In one embodiment, the matching circuits 36, 37, 40,and 41 comprise at least one lump device. In another embodiment, thematching circuits 36, 37, 40, and 41 comprise at least one transmissionline, or comprise at least one balanced to unbalanced transformer.

FIG. 4 shows a block diagram of the first amplifying unit 38 accordingto one embodiment. The first amplifying unit 38 comprises AC couplingcapacitors C₁, C₂, and C₃, a main circuit unit 382, and an assistantcircuit unit 384. Referring to FIG. 4, an input signal in1 is applied tothe main circuit unit 382 and the assistant circuit unit 384 via the ACcoupling capacitors C₁ and C₂, respectively. In one embodiment, the maincircuit unit 382 is an NMOS transistor N₁. The drain terminal of theNMOS transistor N₁ is connected to a power source V_(DD) and to anoutput terminal out1 via the AC coupling capacitors C₃. The sourceterminal of the NMOS transistor N₁ is connected to a reference voltagepotential, and the gate terminal of the NMOS transistor N₁ is connectedto a bias voltage Vbias₁.

As mentioned before, the first amplifying unit 38 conducts during thepositive half-cycle of the input signal in1, while the second amplifyingunit 39 cuts off. At this time, a current I₁ flowing to the outputterminal of the amplifier circuit 30 can be expressed as

$I_{1} = {I_{O}\left\{ {{\frac{1}{2}{\sin ({wt})}} + \left\lbrack {\frac{1}{\pi} - {\frac{2}{\pi}{\sum\limits_{{n = 2},4,\mspace{14mu} \ldots}^{\infty}{\frac{1}{n^{2} - 1}{\cos ({nwt})}}}}} \right\rbrack} \right\}}$

wherein n represents the harmonic number of the combined current I₀.

In contrast, the first amplifying unit 38 cuts off during the negativehalf-cycle of the input signal in1, while the second amplifying unit 39conducts. At this time, a current I₂ flowing to the output terminal ofthe amplifier circuit 30 can be expressed as

$I_{2} = {I_{O}\left\{ {{\frac{1}{2}{\sin ({wt})}} - \left\lbrack {\frac{1}{\pi} - {\frac{2}{\pi}{\sum\limits_{{n = 2},4,\mspace{14mu} \ldots}^{\infty}{\frac{1}{n^{2} - 1}{\cos ({nwt})}}}}} \right\rbrack} \right\}}$

The even-order harmonic of I₀ is suppressed after adding current I₁ andI₂. Therefore, the even-order harmonic of the amplifier circuit 30 canbe suppressed via such architecture. The first and second amplifyingunits 38 and 39 do not turn on at the same time, and thus the directpower consumption of the chip can be reduced.

Referring to FIG. 4, the source terminal current of the NMOS transistorN₁ and the gate terminal to the source terminal voltage (V_(gs)) can beexpressed as

$I_{1} = {I_{O}\left\{ {{\frac{1}{2}{\sin ({wt})}} + \left\lbrack {\frac{1}{\pi} - {\frac{2}{\pi}{\sum\limits_{{n = 2},4,\mspace{14mu} \ldots}^{\infty}{\frac{1}{n^{2} - 1}{\cos ({nwt})}}}}} \right\rbrack} \right\}}$

wherein gm represents a trans-conductance of the NMOS transistor N₁, andgm′ and gm″ are first and second derivatives of the trans-conductance,respectively.

FIG. 6 shows a graph illustrating first and second order derivatives(gm′ and gm″) of the trans-conductance of the NMOS transistor N₁ withrespect to voltage V_(gs). Referring to FIG. 6, gm″ has a positive valuewhen V_(gs) is less than a bias point of the class B amplifier (about0.83V in the figure), and has a negative value when V_(gs) is largerthan the bias point of the class B amplifier. It is known in the artthat gm″ affects a 3rd Inter-Modulation Distortion (IMD3).

Accordingly, the assistant circuit unit 384 is configured to assist thelinearity of the main circuit unit 382. In one embodiment, the assistantcircuit unit 384 is an NMOS transistor N₂. The drain terminal of theNMOS transistor N₂ is connected to the power source V_(DD) and to theoutput terminal out 1 via the AC coupling capacitors C₃. The sourceterminal of the NMOS transistor N₂ is connected to the reference voltagepotential, and the gate terminal of the NMOS transistor N₂ is connectedto a bias voltage V_(th1). The bias voltage V_(th1) is used to adjustthe peak value of the second order derivative of the assistant circuitunit 384 so as to suppress the peak value of the second order derivativeof the main circuit unit 382. In addition, the second order derivativeof the assistant circuit unit 384 can be adjusted by varying the widthto length ratio (W/L) of the NMOS transistor N₂.

FIG. 7 shows a block diagram of the first amplifying unit 38 accordingto another embodiment. In this embodiment, the assistant circuit unit384 comprises a plurality of NMOS transistors N_(2A), N_(2B), and N_(2C)having the same width to length ratio (W/L) as the NMOS transistor N₁.The drain terminal of the NMOS transistors N_(2A), N_(2B), and N_(2C) isconnected to the power source V_(DD). The source terminal of the NMOStransistors N_(2A), N_(2B), and N_(2C) is connected to the referencevoltage potential, and the gate terminal of the NMOS transistors N_(2A),N_(2B), and N_(2C) is connected to the bias voltage V_(th1). Thelinearity of the main circuit unit 382 can be adjusted by varying thenumber of parallel NMOS transistors N_(2A), N_(2B), and N_(2C). Inanother embodiment, the width to length ratio (W/L) of the parallel NMOStransistors N_(2A), N_(2B), and N_(2C) is not the same as the width tolength ratio (W/L) of the NMOS transistor N₁. The linearity of the maincircuit unit 382 can be adjusted by varying the bias voltage Vth1, or byvarying the width to length ratio (W/L) of the parallel NMOS transistorsN_(2A), N_(2B), and N.

FIG. 5 shows a block diagram of the second amplifying unit 39 accordingto one embodiment. The second amplifying unit 39 comprises AC couplingcapacitors C₄, C₅, and C6, a main circuit unit 392, and an assistantcircuit unit 394. Referring to FIG. 5, an input signal in2 is applied tothe main circuit unit 392 and the assistant circuit unit 394 via the ACcoupling capacitors C₄ and C₅, respectively. In one embodiment, the maincircuit unit 392 is a PMOS transistor P₁. The drain terminal of the PMOStransistor P₁ is connected to the power source V_(DD) and to the outputterminal out₂ via the AC coupling capacitors C₆. The source terminal ofthe PMOS transistor P₁ is connected to the reference voltage potential,and the gate terminal of the PMOS transistor P₁ is connected to a biasvoltage Vbias₂.

Referring to FIG. 5, the assistant circuit unit 394 is configured toassist the linearity of the main circuit unit 392. In one embodiment,the assistant circuit unit 394 is a PMOS transistor P₂. The drainterminal of the PMOS transistor P₂ is connected to the power sourceV_(DD) and to the output terminal out2 via the AC coupling capacitorsC₆. The source terminal of the PMOS transistor P₂ is connected to thereference voltage potential, and the gate terminal of the PMOStransistor P₂ is connected to a bias voltage V_(th2). The bias voltageV_(th2) is used to adjust the peak value of the second order derivativeof the assistant circuit unit 394 so as to suppress the peak value ofthe second order derivative of the main circuit unit 392. In addition,the second order derivative of the assistant circuit unit 394 can beadjusted by varying the width to length ratio (W/L) of the PMOStransistor P₂.

In another embodiment, the assistant circuit unit 394 comprises aplurality of PMOS transistors P_(2A), P_(2B), and P_(2C) having the samewidth to length ratio (W/L) as the PMOS transistor P₁. The plurality ofPMOS transistors P_(2A), P_(2B), and P_(2C) are connected in parallel.The linearity of the main circuit unit 392 can be adjusted by varyingthe number of parallel PMOS transistors. In yet another embodiment, thewidth to length ratio (W/L) of the parallel PMOS transistors is not thesame as the width to length ratio (W/L) of the PMOS transistor P₁. Thelinearity of the main circuit unit 392 can be adjusted by varying thebias voltage V_(th2), or by varying the width to length ratio (W/L) ofthe parallel PMOS transistors.

FIG. 8 shows a block diagram of the first amplifying unit 38 accordingto yet another embodiment. In this embodiment, the main circuit unit 382is a PMOS transistor P₃. The drain terminal of the PMOS transistor P₃ isconnected to the power source V_(DD), the source terminal is connectedto the reference voltage potential, and the gate terminal is connectedto the bias voltage Vbias₁. The assistant circuit unit 384 is a PMOStransistor P₄. The drain terminal of the PMOS transistor P₄ is connectedto the power source V_(DD), the source terminal is connected to thereference voltage potential, and the gate terminal is connected to thebias voltage V_(th1). The linearity of the main circuit unit 382 can beadjusted by varying the bias voltage V_(th1), or varying the width tolength ratio (W/L) of the PMOS transistor P₄.

In another embodiment, the assistant circuit unit 384 comprises aplurality of PMOS transistors having the same width to length ratio(W/L) as the PMOS transistor P₃. The plurality of PMOS transistors areconnected in parallel. The linearity of the main circuit unit 382 can beadjusted by varying the number of parallel PMOS transistors.

FIG. 9 shows a block diagram of the second amplifying unit 39 accordingto yet another embodiment. In this embodiment, the main circuit unit 392is an NMOS transistor N₃. The drain terminal of the NMOS transistor N₃is connected to the power source V_(DD), the source terminal isconnected to the reference voltage potential, and the gate terminal isconnected to the bias voltage Vbias₂. Also, the assistant circuit unit394 is an NMOS transistor N₄. The drain terminal of the NMOS transistorN₄ is connected to the power source V_(DD), the source terminal isconnected to the reference voltage potential, and the gate terminal isconnected to the bias voltage V_(th2). The linearity of the main circuitunit 392 can be adjusted by varying the bias voltage V_(th2), or byvarying the width to length ratio (W/L) of the NMOS transistor N₄.

In another embodiment, the assistant circuit unit 394 comprises aplurality of NMOS transistors having the same width to length ratio(W/L) as the NMOS transistor N₃. The plurality of NMOS transistors isconnected in parallel. The linearity of the main circuit unit 392 can beadjusted by varying the number of parallel PMOS transistors.

The present disclosure also discloses an exemplary embodiment of methodfor improving the linearity of the amplifier circuit. In one embodiment,the method first receives an input signal. The first amplifying unit 38conducts in one half cycle of an input signal, and the second amplifyingunit 39 cuts off. The first amplifying unit 38 cuts off in the otherhalf cycle of an input signal, and the second amplifying unit 39conducts. Next, a first control signal is received to adjust thelinearity of the first amplifying unit 38 when the first amplifying unit38 conducts, and a second control signal is received to adjust thelinearity of the second amplifying unit 39 when the second amplifyingunit 39 conducts. In one embodiment, the first control signal is thebias voltage V_(th1), and the second control signal is the bias voltageV_(th2).

FIG. 10(A) shows a simulation result of the output power Pout, gain,power added efficiency (PAE) of the amplifier circuit 30 according toyet another embodiment. FIG. 10(B) shows a comparison result of theamplifier circuit 30 with the prior art 1 and prior art 2 arrangements.The prior art 1 arrangement is a combination of an architecturedisclosed in US publication No. 2006/0049876 with an additionalresonator circuit. The resonator circuit is used to suppress thesecond-order harmonic so as to achieve the same linearity as theamplifier circuit 30. The prior art arrangement 2 is a combination of anarchitecture disclosed in US publication No. 2006/0049876 with twoadditional input and output baluns. The baluns are used to suppress thesecond-order harmonic so as to achieve the same linearity as theamplifier circuit 30. Referring to FIG. 10(B), the PAE of the amplifyingcircuit of an embodiment can increase 10% to 20% compared to the priorart 1 and prior art 2 arrangements.

The above-described exemplary embodiments are intended to beillustrative only. Those skilled in the art may devise numerousalternative embodiments without departing from the scope of thefollowing claims.

1. An amplifier circuit, comprising: a first unit comprising a firstamplifying unit, wherein the first amplifying unit comprises a firstmain circuit unit and a first assistant circuit unit, and the firstassistant circuit unit is configured for assisting a linearity of thefirst main circuit unit; and a second unit comprising a secondamplifying unit, wherein the second amplifying unit comprises a secondmain circuit unit and a second assistant circuit unit, and the secondassistant circuit unit is configured for assisting a linearity of thesecond main circuit unit; wherein the first amplifying unit isconfigured for conducting in one half cycle of an input signal, and thesecond amplifying unit is configured for conducting in the other halfcycle of the input signal.
 2. The amplifier circuit of claim 1, whereinthe first main circuit unit comprises a first transistor, the firstassistant circuit unit comprises at least one second transistor, thesecond main circuit unit comprises a third transistor, and the secondassistant circuit unit comprises at least one fourth transistor.
 3. Theamplifier circuit of claim 2, wherein when the first transistor is anNMOS transistor, at least one second transistor is an NMOS transistor,the third transistor is a PMOS transistor, and the at least one fourthtransistor is a PMOS transistor.
 4. The amplifier circuit of claim 3,wherein the first transistor has a drain terminal connected to a powersource, a source terminal connected to a reference voltage potential,and a gate terminal connected to a first bias voltage; at least onesecond transistor has a drain terminal connected to the power source, asource terminal connected to the reference voltage potential, and a gateterminal connected to a second bias voltage; the third transistor has adrain terminal connected to the power source, a source terminalconnected to the reference voltage potential, and a gate terminalconnected to a third bias voltage; and the at least one fourthtransistor has a drain terminal connected to the power source, a sourceterminal connected to the reference voltage potential, and a gateterminal connected to a fourth bias voltage.
 5. The amplifier circuit ofclaim 2, wherein when the first transistor is a PMOS transistor, the atleast one second transistor is a PMOS transistor, the third transistoris an NMOS transistor, and the at least one fourth transistor is an NMOStransistor.
 6. The amplifier circuit of claim 5, wherein the firsttransistor has a drain terminal connected to the power source, a sourceterminal connected to the reference voltage potential, and a gateterminal connected to a fifth bias voltage; the at least one secondtransistor has a drain terminal connected to the power source, a sourceterminal connected to the reference voltage potential, and a gateterminal connected to a sixth bias voltage; the third transistor has adrain terminal connected to the power source, a source terminalconnected to the reference voltage potential, and a gate terminalconnected to a seventh bias voltage; and the at least one fourthtransistor has a drain terminal connected to the power source, a sourceterminal connected to the reference voltage potential, and a gateterminal connected to an eighth bias voltage.
 7. The amplifier circuitof claim 2, wherein the first transistor is connected to a first nodevia a first alternating current (AC) coupling capacitor, and connectedto a second node via a second AC coupling capacitor.
 8. The amplifiercircuit of claim 2, wherein at least one second transistor is connectedto the first node via a third AC coupling capacitor.
 9. The amplifiercircuit of claim 4, wherein the linearity of the first main circuit unitis adjusted by the second bias voltage, and the linearity of the secondmain circuit unit is adjusted by the fourth bias voltage.
 10. Theamplifier circuit of claim 6, wherein the linearity of the first maincircuit unit is adjusted by the sixth bias voltage, and the linearity ofthe second main circuit unit is adjusted by the eighth bias voltage. 11.The amplifier circuit of claim 2, wherein the linearity of the firstmain circuit unit is adjusted by a width to length ratio of at least onesecond transistor.
 12. The amplifier circuit of claim 2, wherein a widthto length ratio of at least one second transistor is the same as that ofthe first transistor, and the linearity of the first main circuit unitis adjusted by varying the number of second transistors.
 13. Theamplifier circuit of claim 2, wherein the third transistor is connectedto a third node via a fourth AC coupling capacitor, and connected to afourth node via a fifth AC coupling capacitor.
 14. The amplifier circuitof claim 2, wherein the at least one fourth transistor is connected tothe third node via a sixth AC coupling capacitor.
 15. The amplifiercircuit of claim 2, wherein the linearity of the second main circuitunit is adjusted by a width to length ratio of the at least one fourthtransistor.
 16. The amplifier circuit of claim 2, wherein a width tolength ratio of the at least one fourth transistor is the same as thatof the third transistor, and the linearity of the second main circuitunit is adjusted by varying the number of fourth transistors.
 17. Theamplifier circuit of claim 1, wherein the first unit further comprises afirst input matching circuit and a first output matching circuit. 18.The amplifier circuit of claim 1, wherein the second unit furthercomprises a second input matching circuit and a second output matchingcircuit.
 19. A method for improving a linearity of an amplifier circuit,comprising: receiving an input signal; conducting a first amplifyingunit in one half cycle of the input signal and cutting off a secondamplifying unit; cutting off the first amplifying unit in the other halfcycle of the input signal and conducting the second amplifying unit;receiving a first control signal for adjusting a linearity of the firstamplifying unit when the first amplifying unit conducts; and receiving asecond control signal for adjusting a linearity of the second amplifyingunit when the second amplifying unit conducts.
 20. The method of claim19, wherein the first amplifying unit comprises a first main circuitunit and a first assistant circuit unit, and the second amplifying unitcomprises a second main circuit unit and a second assistant circuitunit.
 21. The method of claim 20, wherein the first main circuit unitcomprises a first transistor, the first assistant circuit unit comprisesat least one second transistor, the second main circuit unit comprises athird transistor, and the second assistant circuit unit comprises atleast one fourth transistor.
 22. The method of claim 19, wherein thefirst control signal or the second control signal is a bias voltage. 23.The method of claim 21, wherein the first control signal is used foradjusting a width to length ratio of the at least one second transistor,and the second control signal is used for adjusting a width to lengthratio of the at least one fourth transistor.
 24. The method of claim 21,wherein a width to length ratio of the at least one second transistor isthe same as that of the first transistor, and the first control signalis used for adjusting the number of second transistors.
 25. The methodof claim 21, wherein a width to length ratio of the at least one fourthtransistor is the same as that of the third transistor, and the secondcontrol signal is used for adjusting the number of at least one fourthtransistor.